/* * Zaliczenie * * Created: 22.05.2022 12:02:54 * Author : MichaƂ Turek, Nicol Karbowska */ #include #include #define F_CPU 16000000UL #include #define magistralaDDR DDRB #define magistrala PORTB #define sterowanieDDR DDRC #define sterowanie PORTC #define RS 0 #define E 1 ISR(TIMER1_COMPA_vect){ ADCSRA |= (1<