library ieee;
use IEEE.STD_LOGIC_1164.ALL;
entity zadanie2wer2 is
Port (
input : in std_logic_vector(5 downto 0);
output : out std_logic
);
end zadanie2wer2;
architecture zadanie2wer2 of zadanie2wer2 is
begin
process(input)
variable temp : std_logic;
begin
temp := '1';
for i in input'range loop
temp := temp and not input(i);
end loop;
output <=temp;
end process;
end zadanie2wer2;
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